1. Field of the Invention
The present invention relates to a memory circuit, and more particularly to a memory circuit configured with thin film semiconductor elements. The invention also relates to a display device comprising the memory circuit.
2. Description of the Related Art
In recent years, mobile phones have been widely used with the advance of the communication technology. In the future, transmission of moving images and transmission of a larger amount of information are expected. On the other hand, by reducing the weight of personal computers, those adapted for mobile communication have been produced. Information terminals called PDAs originated in electronic notebooks have also been produced in large quantities and widely used. In addition, most of such portable information equipment includes a flat panel display because of the development of display devices.
Particularly, among active matrix display devices, manufacturing of a display device using a low temperature poly-silicon thin film transistor (hereinafter, a thin film transistor is referred to as a TFT) has been promoted in recent years. By using the low temperature poly-silicon TFT, a signal line driver circuit can be integrally formed around a pixel portion as well as a pixel. Thus, the low temperature poly-silicon TFT allows the compactness and the high definition of a display device and it is expected to be more widely used in the future.
As the one using the low temperature poly-silicon TFT, a controller circuit, a CPU, and a memory circuit in addition to the pixel and the signal line driver circuit have been produced. (For example, Non-patent Document 1)
[Non-Patent Document 1]
Nikkei Electronics, No. 841, Feb. 17, 2003, pp. 123-130
Forming such a logical circuit integrally with a pixel by using a TFT contributes to the formation of a display system on a glass substrate.
A memory circuit is a typical circuit which is required for forming a system. The memory circuit includes a volatile memory circuit such as an SRAM and a DRAM and a nonvolatile memory circuit such as a flash memory and a mask ROM.
The memory circuit comprises a Y decoder 201, a Y selector 202, an X decoder 203, and a memory cell array 204 as shown in FIG. 2. The X decoder 203 selects a word line based on an inputted address signal. The Y decoder 201 selects a switch which is included in the Y selector 202 and connected to a bit line based on an inputted address signal similarly. An address is inputted to the Y decoder 201 and the X decoder 203 so that one memory cell in the memory cell array 204 can be specified and data can be written in or read from the specified memory cell.
Note that the X decoder and the Y decoder are referred to as a row decoder and a column decoder respectively in some cases. They are indicated as an X decoder and a Y decoder in this specification. In addition, a wire in the X direction and a wire in the Y direction which are included in the memory cell array 204 are indicated as a word line and a bit line respectively. The word line is driven by the X decoder 203 in FIG. 2. The X decoder 203, the Y decoder 201, the Y selector 202 and the memory cell array 204 are generally driven by a common power source, a high potential power source of which is indicated as an VDD and a low potential power source thereof is indicated as a VSS in FIG. 2.
A memory element had better have as small memory cell as possible for large memory capacity. It requires the reduction in the number of transistors configuring a memory cell. Each of a mask ROM and a DRAM has a memory cell configured with one transistor while an SRAM has a memory cell configured with six transistors. In addition, such a transistor serves both for writing and for reading. The explanation is made on the case of the SRAM hereinafter.
FIG. 3 shows a memory cell of a conventional SRAM. Only one memory cell 302 is shown in FIG. 3 for simplification, however, the number of memory cells is not limited to one. The memory cell 302 of the SRAM comprises an inverter circuit configured with a TFT 308 and a TFT 310, an inverter circuit configured with a TFT 309 and a TFT 311, and switching transistors 312 and 313.
A writing operation thereof is explained below. When the potential of a specified word line 305 becomes Hi by an X decoder 301, the switching transistors 312 and 313 are turned ON so that data is written in a pair of inverter circuits configured with the TFTs 308 to 311. When the writing is finished, the switching transistors 312 and 313 are turned OFF so that the data which has been written in a pair of inverters is held.
A reading operation is explained next. Firstly, bit lines 303 and 304 are precharged at a certain potential from the outside of the memory cell array. Generally, a precharge potential is set to the nearly middle of a power source of a pair of inverters in a memory cell. After the completion of the precharge, the bit lines 303 and 304 are released from the precharge potential so that the bit lines 303 and 304 are in the floating state. Next, When the potential of the word line 305 becomes Hi and the switching transistors 312 and 313 are turned ON, the bit lines 303 and 304 are each driven in the opposite direction by the pair of inverters and a voltage difference therebetween is detected by a sense amplifier (not shown) so that the data is called out.